The upslot/downslot TDMA frames at the MS and the BS should be synchronized. But the finite propagation delay between the MS and BS causes a mismatch. Therefore, the clock at the MS would have to be advanced by the finite propagation delay time, in order to maintain synchronism. Implementing this would introduce undue complexity. Instead, we work a way around this problem by setting the propagation delay to zero (in ns/wirelessphy.cc).